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1 2.5a regulator with integrated high-side mosfet for synchronous buck or boost buck converter ISL78200 the ISL78200 is a synchronous buck controller with a 90m ? high side mosfet and low side driver integrated. the ISL78200 supports a wide input voltage range from 3v to 40v. regarding the output current capability, th e ISL78200 can typically support a continuous load of 2.5a under conditions of 5v v out , v in range of 8v to 36v, 500khz, +85c ambient temperature with still air. for any specific applic ation, the actual maximum output current depends upon the die temperature not exceeding +125c with the power dissipated in the ic, which is related to input voltage, output voltage, du ty cycle, switching frequency, ambient temperature and board layout, etc. refer to the output current section on page 14 for more details. the ISL78200 has flexible sele ction of operation modes of forced pwm mode and pfm mode. in pfm mode, the quiescent input current is as low as 300a and can be further reduced to 180a with auxvcc connected to v out under 12v v in and 5v v out application. the load boundary between pfm and pwm can be programmed to cover wide applications. the low side driver can be either used to drive an external low side mosfet for a synchronous buck, or left unused for a standard non-synchronous buck. the low side driver can also be used to drive a boost converter as a pre-regulator that greatly expands the operating input voltage range down to 3v or lower (refer to ?typical application schematic iii - boost buck converters? on page 5). the ISL78200 offers the most robust current protections. it uses peak current mode control with cycle-by-cycle current limiting. it is implemented with frequency foldback under current limit condition; in a ddition, the hiccup overcurrent mode is also implemented to guarantee reliable operations under harsh short conditions. the ISL78200 has comprehensive protections against various faults including overvoltage and over-temperature protections, etc. features ? ultra wide input voltage range 3v to 40v ? selectable mode operation - forced pwm mode -pfm mode - programmable current boundary between pfm and pwm modes ? 300a ic quiescent current (pfm, no load); 180a input quiescent current (pfm, no load, v out connected to auxvcc) ? less than 3a standby input current (ic disabled) ? operational topologies -synchronous buck -non-synchronous buck -two stage boost buck ? programmable frequency from 200khz - 2.2mhz and frequency synchronization capability ? 1% tight voltage regulation accuracy ? reliable cycle by cycle overcurrent protection - temperature compensated current sense - frequency foldback - programmable oc limit -hiccup mode protection in worst case short condition ? 20 ld htssop package ? pb-free (rohs compliant) applications ? automotive applications ? general purpose power regulator ? 24v bus power ?battery power ? embedded processor and i/o supplies figure 1. typical application figure 2. efficiency, synchronous buck, pfm mode, v out 5v, t a = +25c v out ISL78200 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood 50 55 60 65 70 75 80 85 90 95 100 0.1m 1m 10m 100m 1 2.5 efficiency (%) load current (a) 6v v in 12v v in 24v v in 40v v in september 22, 2011 fn7641.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL78200 2 fn7641.0 september 22, 2011 pin configuration ISL78200 (20 ld htssop) top view functional pin description pin name pin # description pgnd 1 this pin is used as the ground connec tion of the power flow including driver. boot 2 this pin provides bias voltage to the high-side mosfet driv er. a bootstrap circuit is used to create a voltage suitable to drive the internal n-channel mosfet. the boot charge circuitries are inte grated inside of the ic. no external boot diode is needed. a 1f ceramic capacitor is recommended to be used between boot and phase pin. vin 3, 4 connect the input rail to these pins that are connected to the drain of the integrated hi gh-side mosfet, as well as the source for the internal linear regulator that provides the bias of the ic. range: 3v to 40v. with the part switching, the op erating input voltage applied to the vin pins must be under 40v. this recommendation allows for short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding absolute maximum ratings. sgnd 5 this pin provides the return path for the control and monitor portions of the ic. vcc 6 this pin is the output of the internal linear regulator that supplies the bias fo r the ic including the driver. a minimum 4 .7f decoupling ceramic capacitor is recommended between vcc to ground. auxvcc 7 this pin is the input of the auxilia ry internal linear regulator which can be supplied by the regulator output after pow er-up. with such a configuration, the power dissipation inside the ic is reduced. the inpu t range for this ldo is 3v to 20v. in boost mode operation, this pin works as boost output overvo ltage detection pin. it detects the boost output through a resist or divider. when voltage on this pin is abov e 0.8v, the boost pwm is disabled; and when voltage on this pin is below 0.8v minus the hysteresis, the boost pwm is enabled. range: 3v to 20v. en 8 the controller is enabled when this pin is pulled high. the ic is disabled when this pin is pulled low. range: 0v to 5.5v. fs 9 to connect this pin to vcc, or gnd, or left open will forc e the ic to have 500khz switchin g frequency. the oscillator switch ing frequency can also be programmed by adjust ing the resistor from this pin to gnd. ss 10 connect a capacitor from this pin to ground. this capacitor, along with an internal 5a current source, sets the soft-start interval of the converter. also this pin can be used to track a ramp on this pin. fb 11 this pin is the inverting input of the voltage feedback error amplifier. with a pr operly selected resistor divider connecte d from v out to fb, the output voltage can be set to any voltage between the input rail (reduced by maximum duty cycle and voltage drop) and the 0.8v reference. loop compensation is achieved by connecting an rc network across comp and fb. the fb pin is also monitored for overvoltage events. comp 12 output of the voltage feedback error amplifier. ilimit 13 programmable current limit pin. with this pin connected to vcc pin, or to gnd, or left open, the current limit threshol d is set to default 3.6a; the current limit threshold can be programmed with a resistor from this pin to gnd. mode 14 mode selection pin. pull this pin to gnd for forced pwm mode ; to have it floating or connected to vcc will enable pfm mod e when the peak inductor current is belo w the default threshold of 700ma. the current boundary threshold between pfm and pwm can also be programmed with a resistor at this pin to ground. for more details on pf m mode operation refer to the ?functional description? on page 13. pgood 15 pgood is an open drain output that will be pulled low imme diately under the events when the output is out of regulation (ov or uv) or en pin pulled low. pgood is equipped with a fixed delay of 1000 cycles upon output power-up (v o > 90%). ext_boost phase pgood mode ilimit fb phase comp 11 12 13 14 15 16 17 18 lgate sync 19 20 pgnd boot vin vin sgnd vcc auxvcc en fs ss 1 2 3 4 5 6 7 8 9 10 21 pad
ISL78200 3 fn7641.0 september 22, 2011 phase 16, 17 these pins are the phase nodes that should be connec ted to the output inductor. these pins are connected to the sour ce of the high side n channel mosfet. ext_boost 18 this pin is used to set boost mode and monitor the ba ttery voltage that is the input of the boost converter. after v cc por, the controller will detect the voltage on this pin, if voltag e on this pin is below 200mv, the controller is set in synchronous/non-synchronou s buck mode and latch in this state unless vcc is below the por falling th reshold; if the voltage on this pin after vcc por is above 200mv, the contro ller is set in boost mode and latch in this state. in boost mode, this pin is used to monitor input voltage through a resistor divider. by setting the resistor divider, the high threshold and hysteresis can be programmed. when voltage on th is pin is above 0.8v , the pw m output (lgate) for the boost converter is disabled, and when voltage on this pin is below 0.8v minus the hysteres is, the boost pwm is enabled. in boost mode operation, pfm is disabled when boost pwm is enabled. check boost mode operation in the ?functional description? on page 13 for more details. sync 19 this pin can be used to synchronize two or more ISL78200 controllers. multiple ISL78200 ca n be synchronized with their sy nc pins connected together. 180 degree phase shift is auto matically generated between the master and slave ics. the internal oscillator can also lock to an external frequency source applied on th is pin with square pulse waveform (with frequency 10% higher than the ic?s local frequency, and puls e width higher than 150ns). this pin should be left floating if not used. range: 0v to 5.5v. lgate 20 in synchronous buck mode, this pin is used to drive the lower side mosfet to improve efficiency. in non-synchronous buck when a diode is used as the bottom si de power device, this pin should be connected to vcc before vcc start-up to have low side driver (lgate) disabled. in boost mode, it can be used to drive the boost power mosfet . the boost control pwm is the same with the buck control pwm. pd 21 bottom thermal pad. it is not connected to any electrical potent ial of the ic. in layout it mu st be connected to pcb ground copper plane with an area as large as possib le to effectively reduce the thermal impedance. functional pin description (continued) pin name pin # description ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL78200avez ISL78200 avez -40 to +105 20 ld htssop mdp0048 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL78200 . for more information on msl please see techbrief tb363 .
ISL78200 4 fn7641.0 september 22, 2011 block diagram pgood ss fb boot phase (x2) current monitor mode sgnd en fs comp vcc vin 0.8v reference voltage monitor vin (x2) vcc pgnd auxvcc ocp, ovp, otp pfm logic boost mode control slope compensation lgate ilimit auxilary ldo ea comparator oscillator vcc 5a + + power-on reset soft-start logic sync ext_boost gate drive pfm/fpwm bias ldo boot refresh
ISL78200 5 fn7641.0 september 22, 2011 typical application schematic i figure 3a. synchronous buck fi gure 3b. non-synchronous buck typical application schematic ii - v cc switch over to v out figure 4a. synchronous buck fi gure 4b. non-synchronous buck typical application schematic iii - boost buck converters v out ISL78200 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood v out ISL78200 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood v out ISL78200 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood v out ISL78200 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood v out ISL78200 vcc sgnd mode boot vin phase pgnd fs pgood en ss fb comp auxvcc lgate ilimit + battery ext_boost sync r1 r2 r3 r4 +
ISL78200 6 fn7641.0 september 22, 2011 absolute maximum rating s thermal information vin, phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +44v vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +6.0v auxvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +22v absolute boot voltage, v boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50.0v upper driver supply voltage, v boot - v phase . . . . . . . . . . . . . . . . . . . +6.0v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to vcc + 0.3v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000v latchup rating (tested per jesd78b; class ii, level a) . . . . . . . . . 100ma thermal resistance ja (c/w) jc (c/w) htssop package (notes 4, 5) . . . . . . . . . . . . . . . 35 3.5 maximum junction temperature (plastic package) . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions supply voltage on vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 40v auxvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +20v ambient temperature range (automotive). . . . . . . . . . . . . . .-40c to +105c junction temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications refer to the block diagram (page 4) and typical application schematics (page 5). operating conditions unless otherwise noted: v in = 12v, or v cc = 4.5v, t a = -40c to +105c. typicals are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. parameter symbol test conditions min (note 6) typ max (note 6) units v in supply v in pin voltage range v in pin 3.05 40 v v in connected to vcc 3.05 5.5 v operating supply current i q mode = vcc/floating (p fm), no load at the output 300 a mode = gnd (forced pwm), v in =12v, non-switching 1.2 ma standby supply current i q_sby en connected to gnd, v in = 12v 1.8 3 a internal main linear regulator main ldo v cc voltage v cc v in > 5v 4.2 4.5 4.8 v main ldo dropout voltage v dropout_main v in = 4.2v, i vcc = 35ma 0.3 0.5 v v in = 3v, i vcc = 25ma 0.25 0.3 v v cc current limit of main ldo 60 ma internal auxiliary linear regulator auxvcc input voltage range v auxvcc 320 v aux ldo v cc voltage v cc v auxvcc > 5v 4.2 4.5 4.8 v ldo dropout voltage v dropout_aux v auxvcc = 4.2v, i vcc = 35ma 0.3 0.5 v v auxvcc = 3v, i vcc = 25ma 0.25 0.3 v current limit of aux ldo 60 ma aux ldo switch-over rising threshold v auxvcc_rise auxvcc voltage rise, switch to auxiliary ldo 2.97 3.1 3.2 v aux ldo switch-over falling threshold v auxvcc_fall auxvcc voltage fall, switch back to main bias ldo 2.73 2.87 2.97 v aux ldo switch-over hysteresis v auxvcc_hys auxvcc switch-over hysteresis 0.2 v
ISL78200 7 fn7641.0 september 22, 2011 power-on reset rising v cc por threshold v porh_rise 2.82 2.9 3.05 v falling v cc por threshold v porl_fall 2.6 2.8 v v cc por hysteresis v porl_hys 0.3 v enable required enable on voltage v enh 2 v required enable off voltage v enl 0.8 v oscillator pwm frequency f osc r t = 665k ? 160 200 240 khz r t = 51.1k ? 1950 2200 2450 khz fs pin connected to vcc or floating or gnd 450 500 550 khz min on time t min_on 130 225 ns min off time t min_off 210 325 ns reference voltage reference voltage v ref 0.8 v system accuracy -1.0 1.0 % fb pin source current 5na soft-start soft-start current i ss 3 5 7 a error amplifier unity gain-bandwidth c load = 50pf 10 mhz dc gain c load = 50pf 88 db maximum output voltage 3.6 v minimum output voltage 0.5 v slew rate sr c load = 50pf 5 v/s pfm mode control default pfm current threshold mode = vcc or floating 700 ma internal high-side mosfet upper mosfet r ds(on) r ds(on)_up note 7 90 150 m ? low-side mosfet gate driver lgate source resistance 100ma source current 3.5 ? lgate sink resistance 100ma sink current 3.3 ? boost converter control ext_boost boost_turn-off threshold voltage 0.74 0.8 0.86 v ext_boost hysteresis sink current i auxvcc_hys 2.4 3.2 3.8 a auxvcc boost turn-off threshold voltage 0.74 0.8 0.86 v auxvcc hysteresis sink current i auxvcc_hys 2.4 3.2 3.8 a electrical specifications refer to the block diagram (page 4) and typical application schematics (page 5). operating conditions unless otherwise noted: v in = 12v, or v cc = 4.5v, t a = -40c to +105c. typicals are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
ISL78200 8 fn7641.0 september 22, 2011 power good monitor overvoltage rising trip point v fb/ v ref percentage of reference point 104 110 116 % overvoltage rising hysteresis v fb/ v ovtrip percentage below ov trip point 3 % undervoltage falling trip point v fb/ v ref percentage of reference point 84 90 96 % undervoltage falling hysteresis v fb/ v uvtrip percentage above uv trip point 3 % pgood rising delay t pgood_delay f osc = 500khz 2 ms pgood leakage current pgood high, v pgood = 4.5v 10 na pgood low voltage v pgood pgood low, i pgood = 0.2ma 0.10 v protection default cycle by cycle current limit threshold i oc_1 ilimit = gnd or vcc or floating 3 3.6 4.2 a hiccup current limit threshold i oc_2 hiccup, i oc_2 /i oc_1 115 % overvoltage protection ov latching-off trip point percentage of reference point lg = ug = latch low 120 % ov non-latching-off trip point percentage of reference point lg = ug = low 110 % ov non-latching-off release point percentage of reference point 102.5 % over-temperature protection over-temperature trip point 155 c over-temperature recovery threshold 140 c notes: 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 7. wire bonds not included. the wire bond resistance between vin and phase pin is 32m ? typical. electrical specifications refer to the block diagram (page 4) and typical application schematics (page 5). operating conditions unless otherwise noted: v in = 12v, or v cc = 4.5v, t a = -40c to +105c. typicals are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
ISL78200 9 fn7641.0 september 22, 2011 performance curves figure 5. efficiency, synchronous buck, forced pwm mode, 500khz, v out 5v, t a = +25c figure 6. efficiency, sync hronous buck, pfm mode, v out 5v, t a = +25c figure 7. line regulation, v out 5v, t a = +25c figure 8. load regulation, v out 5v, t a = +25c figure 9. efficiency, synchronous buck, forced pwm mode, 500khz, v out 3.3v, t a = +25c figure 10. efficiency, synchronous buck, pfm mode, v out 3.3v, t a = +25c 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.0 0.5 1.0 1.5 2.0 load current (a) 12v v in 24v v in 40v v in 6v v in efficiency (%) 2.5 50 55 60 65 70 75 80 85 90 95 100 0.1m 1m 10m 100m 1 2.5 efficiency (%) load current (a) 6v v in 12v v in 24v v in 40v v in 4.950 4.952 4.954 4.956 4.958 4.960 4.962 4.964 4.966 4.968 4.970 0 5 10 15 20 25 30 35 40 45 50 input voltage (v) v out (v) i o = 2a i o = 0a i o = 1a 4.950 4.952 4.954 4.956 4.958 4.960 4.962 4.964 4.966 4.968 4.970 0.0 0.5 1.0 1.5 2.0 2.5 load current (a) 6v v in 12v v in 24v v in 40v v in v out (v) 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.0 0.5 1.0 1.5 2.0 2.5 efficiency (%) load current (a) 6v v in 12v v in 24v v in 40v v in 1m 10m 100m 1 2.5 load current (a) efficiency (%) 0.1m 6v v in 12v v in 24v v in 40v v in 40 45 50 55 60 65 70 75 80 85 90 95 100
ISL78200 10 fn7641.0 september 22, 2011 figure 11. input quiescent current under no load, pfm mode, auxvcc connected to v out , v out = 5v figure 12. ic die temperat ure under +105c ambient temperature, 100 cfm, 500khz, v out = 5v, i o = 2a figure 13. ic die temperature under +25c ambient temperature, still air, 500khz, i o = 2a figure 14. ic die temperature under +25c ambient temperature, still air, 500khz, v out = 9v figure 15. synchronous buck mode, v in 36v, i o 2a, enable on figure 16. synchronous buck mode, v in 36v, i o 2a, enable off performance curves (continued) 0 20 40 60 80 100 120 140 160 180 200 -50 -25 0 25 50 75 100 125 input current (a) ambient temperature (c) v in = 40v v in = 24v v in = 12v 105 110 115 120 125 130 135 140 145 150 0 5 10 15 20 25 30 35 40 45 50 ic die temperature (c) v in (v) 25 30 35 40 45 50 55 60 65 70 75 80 85 0 5 10 15 20 25 30 35 40 45 50 v in (v) ic die temperature (c) v out = 5v v out = 12v v out = 20v v out = 9v 25 30 35 40 45 50 55 60 65 70 75 80 85 1.0 1.5 2.0 2.5 i out (a) ic die temperature (c) v in = 40v v in = 12v v in = 24v v out 2v/div 2ms/div phase 20v/div v out 2v/div 2ms/div phase 20v/div
ISL78200 11 fn7641.0 september 22, 2011 figure 17. v in 36v, prebiased start-up figure 18. synchronous buck with force pwm mode, v in 36v, i o 2a figure 19. v in 24v, 0 to 2a step load, force pwm mode figure 20. v in 24v, 80ma load, pfm mode figure 21. v in 24v, 0 to 2a step load, pfm mode figure 22. non-synchronous buck, force pwm mode, v in 12v, no load performance curves (continued) v out 2v/div 2ms/div phase 20v/div v out 20mv/div (5v offset) phase 20v/div 5s/div v out 100mv/div (5v offset) i out 1a/div phase 20v/div 1ms/div v out 1v/div 100s/div v out 70mv/div (5v offset) phase 20v/div lgate 5v/div v out 200mv/div (5v offset) lgate 5v/div i out 1a/div phase 20v/div 1ms/div v out 10mv/div (5v offset) phase 5v/div 20s/div
ISL78200 12 fn7641.0 september 22, 2011 figure 23. non-synchronous buck, force pwm mode, v in 12v, 2a figure 24. boost buck mode, boost input step from 40v to 3v figure 25. boost buck mode, boost input step from 3v to 40v figure 26. boost buck mode, v o = 9v, i o = 1.8a, boost input drops from 16v to 9v dc performance curves (continued) v out 10mv/div (5v offset) phase 10v/div 5s/div v out 1v/div v in _boost 5v/div 20ms/div v out 1v/div v in _boost 5v/div 20ms/div v out 5v/div phase_boost 20v/div 10ms/div il_boost 2a/div phase_buck 20v/div
ISL78200 13 fn7641.0 september 22, 2011 functional description initialization initially, the ISL78200 continually monitors the voltage at en pin. when the voltage on en pin exceeds its rising threshold, the internal ldo will start-up to build up v cc . after power-on reset (por) circuits detect that v cc voltage has exceeded the por threshold, the soft-start will be initiated. soft-start the soft-start (ss) ramp is built up in the external capacitor on the ss pin that is charged by an internal 5a current source. the ss ramp starts from 0v to a voltage above 0.8v. once ss reaches 0.8v, the bandgap reference takes over and the ic goes into steady state operation. the ss plays a vital role in the hiccup mode of operation. the ic works as cycle-by-cycle peak current limiting at overload condition. when a harsh condition occurs and the current in the upper side mosfet re aches the second overcurrent threshold, the ss pin is pulled to ground and a dummy soft-start cycle is initiated. at the dummy ss cycle, the current to charge the soft-start cap is cut down to 1/5 of its normal value. therefore, a dummy ss cycle takes 5 times that of the regular ss cycle. during the dummy ss period, the control loop is disabled and no pwm output. at the end of this cy cle, it will start the normal ss. the hiccup mode persists until the second overcurrent threshold is no longer reached. the ISL78200 is capable of start-up with prebiased output. pwm control pulling the mode pin to gnd will set the ic in forced pwm mode. the ISL78200 employs the peak current mode pwm control for fast transient response and cycl e-by-cycle current limiting. see page 4 for the block diagram. the pwm operation is initialized by the clock from the oscillator. the upper mosfet is turned on by the clock at the beginning of a pwm cycle and the current in th e mosfet starts to ramp up. when the sum of the current sense signal and the slope compensation signal reaches the error amplifier output voltage level, the pwm comparator is triggered to shut down the pwm logic to turn off the high side mosfet. the high side mosfet stays off until the next clock signal comes for the next cycle. the output voltage is sensed by a resistor divider from v out to the fb pin. the difference between the fb voltage and 0.8v reference is amplified and compensated to generate the error voltage signal at the comp pin. then the comp pin signal is compared with the current ramp signal to shut down the pwm. pfm mode operation to pull the mode pin high (>2.5v) or leave the mode pin floating will set the ic to have pfm (pulse frequency modulation) operation in light load. in pfm mode, the switching frequency is dramatically reduced to minimize the switching loss. the ISL78200 enters pfm mode when the mosfet peak current is lower than the pwm/pfm boundary current threshold. this threshold is 700ma as default when there is no programming resistor at mode pin. it can also be programmed by a resistor at the mode pin to ground (see equation 2). where ipfm is the desired pwm/pfm boundary current threshold and r mode is the programming resistor. synchronous and non-synchronous buck the ISL78200 supports both synchronous and non-synchronous buck operations. for a non-synchronous buck operation when a power diode is used as the low side power device, the lgate driver can be disabled with lgate connected to vcc (before ic start-up). input voltage with the part switching, the operating ISL78200 input voltage must be under 40v. this recommendation allows for short voltage ringing spikes (within a couple of ns time range) due to part switching while not exceeding 44v as absolute maximum ratings. output voltage the ISL78200 output voltage can be programmed down to 0.8v by a resistor divider from v out to fb. the maximum achievable voltage is (v in * d max - v drop ), where v drop is the voltage drop in the power path includ ing mainly the mosfet r ds(on) and inductor dcr. the maximum duty cycle d max is decided by (1/fs-t minoff ). c ss f [] 6.5 t ss s [] ? = (eq. 1) r mode 118500 ipfm 0.2 + ---------------------------- - = (eq. 2) 0 100 200 300 400 500 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 r mode (k ? ) ipfm (a) figure 27. r mode vs ipfm
ISL78200 14 fn7641.0 september 22, 2011 output current with the high side mosfet in tegrated, the maximum current ISL78200 can support is decided by the package and many operating conditions including inpu t voltage, output voltage, duty cycle, switching frequency and temperature, etc. first: the maximum dc output current is 5a limited by the package. second: from the thermal perspective, the die temperature shouldn?t be above +125c with the power loss dissipated inside of the ic. figures 12 through 14 show the thermal performance of this part operating at different conditions. the part can output 2.5a under typical application condition v in 8~36v, v o 5v, 500khz, still air and +85c ambient conditions. the output current should be derated under any conditions causing the die temperature to exceed +125c. figure 12 shows a 5v, 2a output application over v in range under +105c ambient temperature with 100 cfm air flow. figure 13 shows 2a applications under +25c still air conditions. different v out (5v, 9v, 12v, 20v) applications thermal data are shown over v in range at +25c and still air. the temperature rise data in this figure can be used to estimate the die temperature at different ambient temperatur es under various operating conditions. note: more temperature rise is expected at higher ambient temperatures due to more conduction loss caused by r ds(on) increase. figure 14 shows thermal performance under various output currents and input voltages. it shows the temperature rise trend with load and v in changes. basically, the die temperature equals the sum of ambient temperature and the temperature rise resulting from power dissipated from the ic package with a certain junction to ambient thermal impedance ja . the power dissipated in the ic is related to the mosfet switching loss, conduction loss and the internal ldo loss. besides the load, these losses are also related to input voltage, output voltage, duty cycle, switching frequency and temperature. with the exposed pad at the bottom, the heat of the ic mainly goes through the bottom pad and ja is greatly reduced. the ja is highly related to layout and air flow conditions. in layout, multiple vias ( 15) are strongly recommended in the ic bottom pad. in addition, the bottom pad with its vias should be placed in ground copper plane with an area as large as possible connected through multiple layers. the ja can be reduced further with air flow. refer to figure 12 for the thermal performance with 100 cfm air flow. boost converter operation the typical application schematic iii on page 5 shows the circuits where the boost works as a pre-stage to provide input to the following buck stage. this is for applications when the input voltage could drop to a very low voltage in some constants (in some battery powered systems as an example), causing the output voltage drops out of regulation. the boost converter can be enabled to boost the input voltage up to keep the output voltage in regulation. when the system input voltage recovers back to normal, the boost stage is disabled while only the buck stage is switching. ext_boost pin is used to set b oost mode and monitor the boost input voltage. at ic start-up befo re soft-start, the controller will latch in boost mode when the voltage on this pin is above 200mv; it will latch in synchronou s buck mode if voltage on this pin is below 200mv. in boost mode, the low-side driver output pwm has the same pwm signal with the buck regulator. in boost mode, the ext_boost pin is used to monitor boost output voltage to turn on and turn off the boost pwm. the auxvcc pin is used to monitor the boost output voltage to turn on and turn off the boost pwm. referring to figure 28, a resistor divider from boost input voltage to the ext_boost pin is used to detect the boost input voltage. when the voltage on the ext_boost pin is below 0.8v, the boost pwm is enabled with a fixed 500 s soft-start when the boost duty cycle increases from t minon *fs to ~50% and a 3a sinking current is enabled at the ext_boost pin for hysteresis purposes. when the voltage on the ext_boost pin recovers to above 0.8v, the boost pwm is disabled immediately. use equation 3 to calculate the upper resistor r up (r1 in figure 28) for a desired hysteresis vhys at boost input voltage use equation 4 to calculate the lower resistor r low (r2 in figure 28) according to a desired boost enable threshold. where vfth is the desired falling threshold on boost input voltage to turn on the boost, 3a is the hysteresis current, and 0.8v is the reference voltage to be compared. note the boost start-up threshold has to be selected in a way that the buck is operating well at cl ose loop before boost start-up. otherwise, large inrush current at boost start-up could occur at boost input due to the buck loop saturation. similarly, a resistor divider from boost output voltage to the auxvcc pin is used to detect the boost output voltage. when the voltage on auxvcc pin is below 0.8v, the boost pwm is enabled with a fixed 500s soft-start, and a 3a sinking current is enabled at auxvcc pin for hysteresis purpose. when the voltage on the auxvcc pin recovers to above 0.8v, the boost pwm is disabled immediately. use equation 3 to calculate the upper resistor r up (r3 in figure 28) according to a desired hysteresis vhy at boost output voltage. use equation 4 to calculate the lower resistor r low (r4 in figure 28) according to a desired boost enable threshold at boost output. r up m [] vhys 3 a [] --------------- - = (eq. 3) r low r up 0.8 ? vfth 0.8 ? ---------------------------- = (eq. 4)
ISL78200 15 fn7641.0 september 22, 2011 assuming vbat is the boost input voltage, v outbst is the boost output voltage and v out is the buck output voltage, the steady state transfer functions are: from equation 5 and equation 6, equation 7 can be derived to estimate the steady state boost output voltage as a function of vbat and vout: after the ic starts up, the boost buck converters can keep working when the battery voltage drops extremely low because the ic?s bias (vcc) ldo is powered by the boost output. for an example of 3.3v output application, when the battery drops to 2v, the vin pin voltage is powered by the boost output voltage that is 5.2v (equation 7), meaning the vin pin (buck input) still needs 5.2v to keep the ic working. note in the above mentioned case, the boost input current could be high because the input voltage is very low (v in *i in =v out *i out * efficiency). if the design is to achieve the low input operation with full load, the inductor and mosfet have to be selected to have enough current ratings to handle the high current appearing at boost input. the boost inductor current are the same with the boost input current, which can be estimated in equation 8, where p out is the output power, vbat is the boost input voltage, and eff is the estimated efficiency of the whole boost and buck stages. based on the same concerns of boost input current, the startup sequence must follow the rule that the ic is enabled after the boost input voltage rise above a certain level. the shutdown sequence must follow the rule that the ic is disabled first before the boost input power source is turned off. at boost mode applications where there is no external control signal to enable/disable the ic, an external input uvlo circuit must be implemented for the startup and shutdown sequence. pfm is not available in boost mode. figure 28. boost converter control auxvcc lgate + battery ext_boost + logic pwm lgate drive 0.8v 0.8v i_hys = 3a i_hys = 3a vout_bst r3 r4 r1 r2 v outbst 1 1d ? ------------ - vbat ? = (eq. 5) v out dv outbst ? d 1d ? ------------ - vbat ? == (eq. 6) v outbst vbat vout + = (eq. 7) il in p out vbat eff ? ----------------------------- = (eq. 8)
ISL78200 16 fn7641.0 september 22, 2011 oscillator and synchronization the oscillator has a default freq uency of 500khz with the fs pin connected to vcc, ground, or floating. the frequency can be programmed to any frequency be tween 200khz and 2.2mhz with a resistor from the fs pin to gnd. with the sync pins simply connected together, multiple ISL78200s can be synchronized. the slave ics automatically have 180 degree phase shift with respect to the master ic. with an external square puls e waveform (with frequency 10% higher than the local frequency, 10% to 90% duty cycle and pulse width higher than 150ns) on th e sync pin, the ISL78200 will synchronize its switching frequency to the fundamental frequency of the input waveform. the internal oscillator synchronizes with the leading edge of the input signal. the rising edge of ugate pwm is delayed by 180 degrees from the leading edge of the external clock signal. fault protection overcurrent protection the overcurrent function protects against any overload condition and output shorts at worst case, by monitoring the current flowing through the upper mosfet. there are 2 current limiting thresholds. the first one, i oc1 , is to limit the high-side mosfet peak current cycle-by-cycle. the current limit threshold is set to de fault at 3.6a with the ilimit pin connected to gnd or vcc, or left open. the current limit threshold can also be programmed by a resistor, r lim , at the ilimit pin to ground. use equation 10 to calculate the resistor. note that with the lower r lim , i oc1 is higher. i oc1 reaches its maximum 5.4a with r lim at 54.9k (typ), the oc limit goes to its default value of 3.6a (typ). the second current protection threshold, i oc2 , is 15% higher than i oc1 mentioned above. at the instant the high-side mosfet current reaches i oc2 , the pwm shuts off after a 2 cycle delay and the ic enters hiccup mode. in hiccup mode, the pwm is disabled for a dummy soft-start duration equal to 5 regular soft-start periods. after this dummy soft-start cycle, the true soft-start cycle is attempted again. the i oc2 offers a robust and reliable protection against worst case conditions. the frequency fold ba ck is implemented for the ISL78200. when overcurrent limiting, the switching frequency is reduced to proportional to the output voltage in order to keep the inductor current under the limit threshold during overload condition. the low limit of frequency under frequency foldback is 40khz. overvoltage protection if the voltage detected on the fb pin is over 110% of reference, the high-side and low-side driv ers shut down immediately and won?t be allowed on until the fb voltage falls down to 0.8v. when the fb voltage drops to 0.8v, the drivers are released on. if the 120% overvoltage threshold is reached, the high-side and low-side driver shut down immediately and the ic is latched off. the ic has to be reset for restart. thermal protection the ISL78200 pwm will be disabled if the juncti on temperature reaches +155c. a +15c hysteresis insures that the device will not restart until the junction temperature drops below +140c. component selections output capacitors output capacitors are required to filter the inductor current and supply the load transient current. all ceramic output capacitors are achievable with this ic. also, in applications the aluminum electrolytic type capacitor provides better load transient and longer holdup time for the load. when low cost, high esr aluminum capacitors are used at the output, a ceramic capacitor (2.2f to 10f) is recommended to handle the ripple current and reduce the total equivalent esr effectively. r fs k [] 145000 16 fs ? khz [] ? fs khz [] ------------------------------------------------------------- - = (eq. 9) figure 29. r fs vs frequency 0 400 1200 0 1000 1500 2500 r fs (k ? ) f s (khz) 1000 800 600 200 500 2000 r lim 300000 i oc a [] 0.018 + -------------------------------------- - = (eq. 10) 70 120 170 220 270 320 370 0.0 1.0 2.0 3.0 4.0 5.0 6.0 figure 30. r lim vs i oc1 r lim (k ? ) i oc1 (a)
ISL78200 17 fn7641.0 september 22, 2011 input capacitors depending upon the system input power rail conditions, the aluminum electrolytic type capacitor is normally needed to provide the stable input voltag e and restrict the switching frequency pulse current in small areas over the input traces for better emc performance. the input capacitor should be able to handle the rms current from the switching power devices. ceramic capacitors must be used at the vin pin of the ic and multiple capacitors including 1f and 0.1f are recommended. place these capacitors as closely as possible to the ic. output inductor generally the inductor should filter the current ripple to 30~40% of the regulator?s maximum average output current. the low dcr inductor should be selected for the highest efficiency. also, the inductor saturation current rati ng should be higher than the highest transient expected. low side power mosfet in synchronous buck application, a power n mosfet is needed as the synchronous low side mosfet and it must have low r ds(on) , lowest rg (rg_typ < 1.5 ? recommended ) , vgth (vgth_min 1.2v) and qgd. a good example is bsz100n06ls3g. output voltage feedback resistor divider the output voltage can be programmed down to 0.8v by a resistor divider from v out to fb according to equation 11. in applications requiring the le ast input quiescent current, large resistors should be used for th e divider to keep its leakage current low. 232k is a recommended for the upper resistor. compensation network with peak current mode control, type ii compensation is normally used for most of applic ations. however, in applications seeking to achieve higher bandwidth, type iii compensation is good to use. note in applications where the pfm mode is desired, and type iii compensation network is used, the value of the capacitor between the comp pin and the fb pi n (not the capacitor in series with the resistor between comp and fb) should be minimal to reduce the noise coupling for proper pfm operation. 10pf is recommended for this capacitor between comp and fb at pfm applications. a capacitor (<1nf) at the fb pin to ground also helps proper pfm mode operation. boost inductor besides the need to sustain the current ripple to be within a certain range (30% to 50%), the boost inductor current at its soft-start is a more important pe rspective to be considered in selection of the boost inductor. each time the boost starts up, there is a fixed 500s soft-start time when the duty cycle increase linearly from t minon to ~50%. before and after boost start-up, the boost output voltage will jump from v in _boost to voltage (v in _boost+v out _buck). the design target in boost soft-start is to ensure the boost input current is sustained to a minimum but capable of charging the boost output voltage to have a voltage step equaling to v out _buck. a big inductor will block the inductor current increase and not high enough to be able to charge the output capacitor to the final steady state value (v in _boost+v out _buck) within 500s. a 6.8h inductor is a good starting point for its selection in design. the boost inductor current at start-up must be checke d by an oscilloscope to ensure it is under the acceptable range. boost output capacitor based on the same theory in boost start-up described above in boost inductor selection, a large capacitor at boost output will cause high inrush current at boos t pwm start-up. 22f is a good choice for applications with buck output voltage less than 10v. also, some minimum amount of capacitance has to be used in boost output to keep the system stable. layout suggestions 1. put the input ceramic capacitors as close to the ic vin pin and power ground connecting to the power mosfet or diode. keep this loop (input ceramic capacitor, ic v in pin and mosfet/diode) as tiny as po ssible to achieve the least voltage spikes induced by the trace parasitic inductance. 2. put the input aluminum capacitors close to ic vin pin. 3. keep the phase node copper area small but large enough to handle the load current. 4. put the output ceramic and aluminum capacitors also close to the power stage components. 5. put vias ( 15) in the bottom pad of the ic. the bottom pad should be placed in the ground copper plane with an area as large as possible in multiple layers to effectively reduce the thermal impedance. 6. place the 4.7f ceramic decoupling capacitor at the vcc pin and as close as possible to the ic. put multiple vias ( 3) close to the ground pad of this capacitor. 7. keep the bootstrap capacitor close to the ic. 8. keep the lgate drive trace as short as possible and try to avoid using a via in the lgate drive path to achieve the lowest impedance. 9. place the positive voltage sense trace close to the load for tighter regulation. 10. place all the peripheral control components close to the ic. v out 0.8 1 r up r low --------------- + ?? ?? ?? ? = (eq. 11) figure 31. pcb via pattern
ISL78200 18 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7641.0 september 22, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL78200 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change september 22, 2011 fn7641.0 initial release
ISL78200 19 fn7641.0 september 22, 2011 htssop (heat-sink tssop) family n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane bottom view exposed thermal pad e2 d1 mdp0048 htssop (heat-sink tssop) family symbol millimeters tolerance 14 ld 20 ld 24 ld 28 ld 38 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.075 0.075 0.075 0.075 0.075 0.075 a2 0.90 0.90 0.90 0.90 0.90 +0.15/-0.10 b 0.25 0.25 0.25 0.25 0.22 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 6.50 7.80 9.70 9.70 0.10 d1 3.2 4.2 4.3 5.0 7.25 reference e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e2 3.0 3.0 3.0 3.0 3.0 reference e 0.65 0.65 0.65 0.65 0.50 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference n 1420242838reference rev. 3 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.

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